This invention relates to the design, layout, testing and manufacture of microelectronic circuits and systems, and more particularly to apparatus and methods for verifying microelectronic circuits and systems prior to manufacture.
Present day ultra-large-scale integration (ULSI) circuits may include hundreds of thousands or millions of interconnected active electronic devices on an integrated circuit chip. The large capital investment required to fabricate and test large scale integrated circuits prior to sale to a customer and the difficulty, expense and loss of goodwill associated with reworking and replacing integrated circuits which fail to operate as planned, have increased the need to accurately characterize the electrical behavior of integrated circuits prior to their manufacture.
Moreover, now that submicron and deep-submicron (0.5 xcexcm and below) technologies have begun to dominate silicon chip manufacturing and the prospect of million-plus-gate chips operating at clock rates of 100 MHZ has become a reality, fundamental changes have had to be made to conventional integrated circuit design methodologies and the electronic design automation (EDA) tools based thereon. To meet the challenges posed by such large-scale circuits, techniques have been developed to represent integrated circuit designs at various levels of abstraction. According to these techniques, an integrated circuit design may be represented by an electrical schematic containing devices and nets interconnecting the devices and by geometric layout data that describes patterns of regions or elements to be formed in and/or on an integrated circuit substrate (e.g., wafer). These patterns, which can be represented textually in software, are also frequently represented as colored polygons when viewed on a computer-aided-design (CAD) tool display.
Techniques for managing highly integrated circuit designs include hierarchical design techniques. Using such techniques, a particular design can be partitioned into functional cells and cells-within-cells, etc., so that at a given level of hierarchy the design may be analyzed as a set of cells and their respective interconnections, without being concerned with all the details of the contents of the cells (e.g., subcells within each cell).
These hierarchical techniques can be essential to the efficient performance of computer-assisted integrated circuit design verification. Such verification may include operations to perform hierarchical layout versus schematic comparison (LVS) and post-layout verification using hierarchical design rule checking (DRC) operations and other post-layout verification operations. Exemplary tools for performing post-layout verification operations are described more fully in commonly assigned U.S. Pat. No. 5,896,300 to Raghavan et al., entitled xe2x80x9cMethods, Apparatus and Computer Program Products for Performing Post-Layout Verification of Microelectronic Circuits By Filtering Timing Error Bounds for Layout Critical Netsxe2x80x9d, the disclosure of which is hereby incorporated herein by reference. An exemplary tool for performing LVS comparison is also more fully described in commonly assigned U.S. Pat. No. 6,009,252 to Lipton, entitled xe2x80x9cMethods, Apparatus and Computer Program Products for Determining Equivalencies Between Integrated Circuit Schematics and Layouts Using Color Symmetrizing Matricesxe2x80x9d, the disclosure of which is hereby incorporated by reference.
A conventional technique for performing design rule checking (DRC) is described in U.S. Pat. No. 6,115,546 to Chevallier et al., entitled xe2x80x9cApparatus and Method for Management of Integrated Circuit Layout Verification Processesxe2x80x9d. This technique performs operations to access a database upon completion of a DRC or LVS operation and queries a user as to whether a cell should be marked as successfully passing the appropriate verification procedure. A user is also able to access a report generating module to inspect the verification status of a cell in the IC design and generate a report showing the status of the verification procedures for each cell, organized according to one of several criteria. Another conventional technique for performing design rule checking is described in U.S. Pat. No. 6,011,911 to Ho et al., entitled xe2x80x9cLayout Overlap Detection With Selective Flattening In Computer Implemented Integrated Circuit Designxe2x80x9d. In this technique, when instances of cells overlap, an overlap area is determined using predefined data structures that divide each cell into an array of spatial bins. Each bin associated with a parent cell is examined to determine if two or more cell instances reside therein or if a cell instance and local geometry reside therein. Once overlap is detected, the areas of the layout data corresponding to the overlap areas are selectively flattened prior to DRC and LVS processing.
Other techniques for performing DRC operations on layouts of highly integrated circuits include identifying portions of a layout where one or more design rules are not to be checked when a DRC operation is performed on the layout. Unfortunately, this technique typically requires manual identification within the layout of each instance where a particular design rule is not to be checked. For example, this technique may require the manual editing of a cell to include a polygon covering a particular region where a DRC violation is present or anticipated and then NOTing away any design rule check of this particular region when the DRC operation is performed. This manual identification process can be very time consuming, particularly when an instance applies to a highly repetitive structure such as a memory cell within an highly integrated memory cell array. Thus, notwithstanding these conventional techniques for verifying integrated circuit layouts for compliance with design rules, there continues to be a need for more efficient techniques for verifying integrated layouts.
Embodiments of the present invention enable a user to automatically waive, or disregard, selected dimensional check violations when running design rule checking operations on integrated circuit layouts. This automatic waiver option is provided by the use of one or more waiver layout patterns (e.g., waiver xe2x80x9ccellsxe2x80x9d) that are preferably evaluated after a suspected DRC violation has been identified. In particular, each of the waiver layout patterns is preferably designed to address a respective dimensional check violation that would otherwise be identified as a confirmed DRC violation (i.e., violation of a respective DRC rule) at the conclusion of a DRC operation. Waiving one or more design rule violations may be advantageous in those circumstances where a portion of a layout containing a known xe2x80x9ctechnicalxe2x80x9d violation of a design rule is also known to yield acceptable performance when manufactured. This is particularly true when the xe2x80x9ctechnicalxe2x80x9d violation is within a child cell (e.g., memory cell) that is replicated numerous times within a larger hierarchical design and, therefore, when generating a file highlighting these numerous technical violations would be cumbersome for a user to review and evaluate.
According to a first preferred method of checking an integrated circuit layout for design rule violations, an operation is performed to determine a match between a waiver layout pattern and a first portion of an integrated circuit layout containing a suspected violation of a first design rule. This operation is preferably performed automatically during a comprehensive DRC operation on the entire integrated circuit layout. Each violation of a design rule is preferably treated initially as a xe2x80x9csuspectedxe2x80x9d violation prior to an operation to compare one or more different waiver layout patterns to the portion of the integrated circuit containing the xe2x80x9csuspectedxe2x80x9d violation. A failure to identify a match with any of the waiver layout patterns operates to convert the xe2x80x9csuspectedxe2x80x9d violation into a xe2x80x9cconfirmedxe2x80x9d violation. At the end of the comprehensive DRC operation, separate files may be generated that list each of the occurrences of the suspected violations that have been waived and the confirmed violations that have not been waived.
According to another preferred method of verifying an integrated circuit layout, operations are performed to evaluate an integrated circuit layout to determine a plurality of suspected violations of design rules, and to determine if a match exists between a waiver layout pattern and a portion of the integrated circuit layout that includes a first suspected violation from within the plurality of suspected violations. A plurality of confirmed violations of the design rules are then determined as a subset of the plurality of suspected violations by omitting the first suspected violation if a match has been determined. The operation to determine a match preferably includes operations to determine whether each and every critical edge of the waiver layout pattern can be mapped to a respective edge in the integrated circuit layout, regardless of orientation. Typically, a violation may only be waived when each and every edge that is entirely within an extent of the waiver layout pattern can be mapped to a respective edge in a portion of the integrated circuit layout containing the suspected violation. A dummy layout pattern may be used to define a larger extent of the waiver layout patterns and increases the number of edges that may be treated as critical edges. Embodiments of the present invention also include computer-program products embodying instructions that can be processed to perform the preferred operations, as well as computer-aided design tools that include hardware and software to perform the preferred operations.